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New Conception and Algorithm of Allocation Mapping for Processor Arrays Implemented into Multi-Context FPGA Devices

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Executive Summary

In this paper, the authors present new concept of realization of algorithms with regular graphs of information dependencies, in form of systolic arrays realized in multi-context programmable devices. Processor matrix efficiency depends on both allocation and schedule mapping. Authors use evolution algorithms and constraint programming to determine allocation mapping and optimize run-time of set algorithm. The authors compared the run-time of Cholesky's algorithm for banded matrices in which the new concept has been used with ones obtained by use of linear and non-linear allocation mapping for processor matrix.

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