Date Added: Oct 2009
In this paper, the authors present new concept of realization of algorithms with regular graphs of information dependencies, in form of systolic arrays realized in multi-context programmable devices. Processor matrix efficiency depends on both allocation and schedule mapping. Authors use evolution algorithms and constraint programming to determine allocation mapping and optimize run-time of set algorithm. The authors compared the run-time of Cholesky's algorithm for banded matrices in which the new concept has been used with ones obtained by use of linear and non-linear allocation mapping for processor matrix.