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CMOS technology has continuously scaled into deep sub-micron regime. With CMOS scaling, many complex design issues arise. The challenges include, but not limited to, the increasing of interconnect delay and power, exponential growth of leakage power, and rapid growth of design complexity. These challenges motivate the authors to design new CAD algorithms to reduce power consumption (both leakage power and dynamic power), to effectively reduce design complexity, and to improve circuit performance. In this paper, the authors present a floorplanning algorithm for 3-D IC designs, which can effectively reduce interconnect delays. The algorithm is based on a generalization of the classical 2-D slicing floorplans to 3-D slicing floorplans.
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