Novel Design of a 9T SRAM Cell With Reduced Leakage for Embedded Cache Memory Application
Low power memory design is one of the most challenging aspects in VLSI design. Trends in scaling technology have led to domination of leakage power dissipation. With large number of low power techniques being adopted for logic circuits, it is required to design low power SRAM cells that can reduce leakage power dissipation. In this paper, a novel 9T SRAM cell is designed and optimized for low leakage power using data retention gated ground logic and drowsy logic. The area optimization is achieved by introducing symmetry in the 9T SRAM cell. Leakage power is reduced by 45% and 20% area optimization is achieved. The designed cell is modeled using 65nm process technology and verified using Hspice.