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In this paper, the authors present a novel and efficient technique to model WiMAX multimode interleaver using hardware description language. The hardware model is implemented on FPGA platform. The authors proposed interleaver consists of finite state machine based address generator and optimized FPGA's embedded resource based memory. The finite state machine based address generator of the interleaver shows better performance in terms of maximum operating frequency, and FPGA resource utilization compared to existing FPGA techniques. Use of FPGA's embedded memory offers advantages like reduced access time, lesser real estate occupancy of circuit board and lower power consumption than external memory based techniques.
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