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Different Intellectual Property (IP) cores, including processor and memory, are interconnected to build a typical System-on-Chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip (NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale Systems-on-Chip (SoC) design. The authors proposed an idea on building customizing synthesis network-on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, they did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, they observed that the overall latency and throughput of the EBFT is better compared to other topologies.
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