Processors

Nurture IDR Segmentation and Multiple Instruction Queues in Superscalar Pipelining Processor

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Executive Summary

This paper proposes a model which improves the speed of the pipelining mechanism therefore increasing the speed of the processor. Superscalar operation is used to get maximum throughput from the processor using the pipelining concept. This proposal can be considered as the advancement of the super scalar property in pipelining which presently exists. The authors introduce a concept, using multiple instruction queues and a new unit called as Identifier unit. The Identifier unit is designed as having the ability of the identifying the type of the instruction which is being fetched and separating it based on its types thus creating separate segments of execution, which in turn increases the speed of the processor.

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