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This paper presents an approach to on-chip memory sub-system architecture for image compression algorithms especially for data dependent applications. The proposed memory sub-system reduces the access latency and power by identifying the frequently reused data and buffered in it. It is capable of identifying re-used data irrespective of irregular memory access pattern. This memory subsystem is employed with a cluster of cache and Scratch Pad Memory (SPM). The efficiency of the proposed system is verified for parallel computations, in case of irregular memory array access pattern. It consumes less power and execution time compared to SPM alone. Further a comparative study of the proposed memory sub-system for various cache-hit ratios is analyzed.
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