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This paper discusses the work done by the author and his coworkers in the area of self-checking and fault tolerant FPGA design. It also proposes an FPGA architecture that is composed of functional cells with built in error correction capability. A functional cell in the proposed architecture can be used to implement logic functions as well as to route signals to other functional cells. It is composed of three units: a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell.
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