On the Design of Low-Power Cache Memories for Homogeneous Multi-Core Processors

This paper investigates the impact of Level-1 Cache (CL1) parameters, Level-2 Cache (CL2) parameters, and cache organizations on the power consumption and performance of multi-core systems. The authors simulate two 4-core architectures - both with private CL1s, but one with shared CL2 and the other one with private CL2s. Simulation results with MPEG4, H.264, matrix inversion, and DFT workloads show that reductions in total power consumption and mean delay per task of up to 42% and 48%, respectively, are possible with optimized CL1s and CL2s.

Provided by: Institute of Electrical and Electronics Engineers Topic: Data Centers Date Added: Feb 2010 Format: PDF

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