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As proscribed by Moore's law, the size of integrated circuits has grown geometrically, resulting in simulation becoming the major bottleneck in the circuit design process. Parallel simulation provides them with a way to cope with this growth. In this paper, the authors describe an optimistic (time warp) parallel discrete event simulator which can simulate all synthesizeable Verilog circuits. They investigate its scalability and describe a machine learning based dynamic load balancing algorithm for use with the simulator. They initially developed two dynamic load balancing algorithms to balance the load and the communication, respectively, during the course of a simulation.
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