On the Scalability of Parallel Verilog Simulation

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As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this paper, the authors examine the performance of a parallel Verilog simulator on four large, real designs. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. They develop a parser for Verilog files enabling them to simulate in parallel all synthesizable Verilog circuits.