Hardware

Optimal Placement of Processors Based on Effective Communication Load

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Executive Summary

This paper presents a new technique for the optimum placement of processors to minimize the total effective communication load under multi-processor communication dominated environment. This is achieved by placing heavily loaded processors near each other and lightly loaded ones far away from one another in the physical grid locations. The results are mathematically proved for the Algorithms are described. In this paper, the authors consider the efficiency of communication as the main criterion while placing the VLSI blocks (Processors). When several processors are to be placed in a grid lay out, their location can be chosen to minimize the overall effective Communication Load among them. This maximizes the total traffic transportation in a given time.

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