Optimized Architecture of Low Power, High Performance Multiplier for Crypto Chips

Date Added: Jul 2011
Format: PDF

The paper presents unified Architecture of an efficient and Low Power Multiplier that can support multiplication based on Galois Fields GF (2m). Cryptography Algorithms involve extensive multiplication for encryption and decryption of data using Diffe-Hellman (DH) Key exchange protocol, RSA and Elliptical Curves cryptography. These can be effectively achieved by hardware implementation with very high speed operations, almost more than 100 times faster compared to software implementation. The hardware computation of algorithms is much better compared to software implementation since it reduces the computation time overhead and can perform better in the application in Real time embedded systems.