Hardware

Optimized Test Scheduling With Reduced Wrapper Cell for Embedded Core Testing

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Executive Summary

The increasing Design for Test (DfT) area overhead and potential performance degradation is caused due to wrapping all the embedded cores for modular System-on-Chip (SoC) testing. This paper proposes a solution for reducing the number of Wrapper Boundary Register (WBR) cells. By utilizing the WBRs of the surrounding cores to transfer test stimuli and responses, the WBRs of some cores can be removed without affecting the testability of the SoC. The authors denote the cores without WBRs as light-wrapped cores and present a new modular SoC test architecture for concurrently testing both the wrapped and the light-wrapped logic cores.

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