Processors

Optimizing Non-Sequential Data Processing Applications

Free registration required

Executive Summary

Data processing applications that manage large numbers of data flows, either by indexing or pointer chasing, may be subject to frequent instruction pipeline stalls due to data cache misses. This paper outlines techniques for use on Intel Architecture processors to lessen the effect of instruction pipeline stalls in certain application designs. It is assumed that the reader is familiar with the 'C' programming language, IA-32 assembly language, and the GNU 'C' Compiler (GCC).

  • Format: PDF
  • Size: 140.19 KB