Optimizing the HW/SW Boundary of an ECC SoC Design Using Control Hierarchy and Distributed Storage

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Executive Summary

Hardware/Software codesign of Elliptic Curve Cryptography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware, and not on the system integration into SoC architecture. The authors study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become performance limited due to coprocessor data- and instruction-transfers. A dual strategy is proposed to remove the bottleneck: Introduction of local control as well as local storage in the coprocessor.

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