Optimum Body Biasing Technique in Domino Logic Gate Design for Low Power Applications
Domino CMOS logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this paper, AND gates with different body biasing are compared taking power consumption and delay as parameters. The designs are tested in 32nm technology. The domino AND gate design with least power consumption, delay and power delay product is proposed.