Packet-Level Static Timing Analysis for NoCs

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Executive Summary

Networks-on-Chip (NoCs) are used in a growing number of SoCs and multi-core processors, increasing the need for accurate and efficient modeling to aid the design of integrated systems. A methodology for packet-level static timing analysis in NoCs is presented. It enables quick and accurate gauging of the performance parameters of a virtual-channel wormhole NoC without using simulation techniques. The network model can handle any topology, link capacities, and buffer capacities. It provides per flow analysis that is orders-of-magnitude faster than simulation while being both significantly more accurate and more complete than prior static modeling techniques.

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