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The era of bus-dominated communication architectures for SoCs might end soon: the increasing number of cores used on a single die used in response to the power-hungry applications tends to make SoC designs more and more communication-centric. Communication structure synthesis is an increasingly challenging problem; bus-based structures are still leading but tend to become the cornerstone of successful SoC designs: among others issues, they hardly allow parallel communications and scale badly from the electrical point of view. Based on a previously published Network-on-Chip, this paper presents and discusses the performance/cost tradeoffs achieved through different hardware solutions, like Quality of Service (QoS) support.
- Format: WORD
- Size: 221 KB