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Pipelined SRAM-based algorithmic solutions have become competitive alternatives to TCAMs (Ternary Content Addressable Memories) for high throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over different pipelines as well as across different stages of each pipeline must be balanced. Second, the traffic among these pipelines should be balanced. Third, the intra-flow packet order should be preserved. In this paper, the authors propose a parallel SRAM-based multi-pipeline architecture for IP lookup.
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