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Parallel LDPC Decoder Implementation on GPU Based on Unbalanced Memory Coalescing

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Executive Summary

The authors consider flexible decoder implementation of Low Density Parity Check (LDPC) codes via Compute-Unified-Device Architecture (CUDA) programming on Graphics Processing Unit (GPU), a research subject of considerable recent interest. An important issue in LDPC decoder design based on CUDA-GPU is realizing coalesced memory access, a technique that reduces memory transaction time considerably. In previous works along this direction, it has not been possible to achieve coalesced memory access in both the read and write operations due to the asymmetric nature of the bipartite graph describing the LDPC code structure.

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