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The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed, low power and reduced layout area. A cell which is functional at the nominal supply voltage, can fail at a lower voltage. From a system perspective this leads to a higher bit-error rate with voltage scaling and limits the opportunity for power saving. While this is a serious bottleneck for SRAM arrays used for data storage. This paper presents a performance analysis of reconfigurable SRAM cell for low power application.
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