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The authors consider a new generation of COTS Software Routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Their main objective is to analyze, to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR behavior and networking performance. To this purpose, they tried to understand and to separately characterize the roles of both HW and SW layers through a large set of internal and external experimental measures, obtained with a heterogeneous set of HW platforms and SR setups.
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