Date Added: Jun 2010
In this paper, the authors present an approach for studying the design space when interfacing reconfigurable accelerators with a CPU. For this purpose they introduce a framework based on the LLVM infrastructure that performs hardware/software partitioning with runtime estimation utilizing profiling information and code analysis. They apply it to reconfigurable accelerators that are controlled by a CPU via a direct low-latency interface but also have direct access to the memory hierarchy. Their results show that a shared L2 cache for CPU and accelerator seems to be the most promising design point for a range of applications.