Performance Evaluation of Adaptive Routing Algorithms for Achieving Fault Tolerance in NoC Fabrics

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Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single System on Chip (SoC) currently, and the number is likely to increase significantly in the near future. The communication requirements of these large Multi Processor SoCs (MP-SoCs) are convened by the emerging Network-on-a-Chip (NoC) paradigm. In the Deep Sub-Micron (DSM) VLSI processes, it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing faults. To become a viable alternative IC design methodology the NoC paradigm must address the system-level reliability issues, which is going to be the dominant concern in the DSM and beyond silicon era.