Processors

Performance Evaluation of Dynamic Speculative Multithreading With the Cascadia Architecture

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Executive Summary

Thread-Level Parallelism (TLP) has been extensively studied in order to overcome the limitations of exploiting Instruction-Level Parallelism (ILP) on high-performance superscalar processors. One promising method of exploiting TLP is Dynamic Speculative Multi-Threading (D-SpMT), which extracts multiple threads from a sequential program without compiler support or instruction set extensions. This paper introduces Cascadia, a D-SpMT multicore architecture that provides multigrain thread-level support and is used to evaluate the performance of several benchmarks. Cascadia applies a unique sustainable IPC (sIPC) metric on a comprehensive loop tree to select the best performing nested loop level to multi-thread.

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