Performance Evaluation of FPM on Spartan Family FPGas and Analyze Its Effect on Bonded IOBs
VHDL programming for IEEE single precision floating point multiplier module have been explored because floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, the main emphasis is on the implementing it effectively such that it uses less combinational delay with high Speed. Floating point operations are hard to implement on FPGAs i.e., on reconfigurable hardware's because of their complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high level of accuracy in their calculations.