Performance Evaluation of Three Network-on-Chip (NoC) Architectures
As the number of processing elements which can be placed on a single chip doubles about every two years, both System-on-Chip (SoC) and the microprocessor market call for high-performance, flexible, scalable, and design-friendly interconnection network architectures. Network-on-Chip (NoC) has been proposed as a solution to multi-core communication problems. The advantages of NoC include high bandwidth, low latency, low power consumption and scalability. The interconnection architecture has a significant impact on the performance of networks in terms of point-to-point delay, throughput, and loss rate.