Performance Improved Router Design Using Hardware Routing Methodology
Network-on-Chip (NoCs) have emerged as a promising on-chip interconnect for future multi/many-core architectures as NoCs are able to scale communication links with the growing number of cores. In this paper, the authors address these problems with a runtime Adaptive Network-on-Chip (AdNoC). Focusing on the architecture-level adaptation, they present an adaptive route allocation algorithm which provides a required level of QoS (guaranteed bandwidth) coupled with an adaptive buffer assignment scheme which reassigns buffer blocks on-demand. Moreover, the area overhead is also reduced by resource multiplexing due to the on-demand buffer assignment at each output port. The Proposed Router Architecture can be designed using Verilog HDL, synthesized using Xilinx Project Navigator tool and implemented in FPGA XCS3S500E.