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Execution of applications on upcoming High-Performance Computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will be composed of a large number of "Fat" nodes, where each node consists of multiple processors on a chip with symmetric multithreading capabilities, interconnected via high-performance networks. Traditional system software for parallel computing considers these Chip Multiprocessors (CMPs) as arrays of symmetric multiprocessing cores, when in fact there are fundamental differences among them. Opportunities for optimization on CMPs are lost using this approach.
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