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In this paper, the authors address a known hard problem - closing the gap between custom and semicustom VLSI design styles and the ASIC VLSI design style - critical to the effective design of large modern CPUs. One particularly challenging aspect of this problem is the placement of latches to improve both signal timing and clock-network power. To this end, the authors propose a new strategy to mitigate and eliminate disruptive changes in physical synthesis that impact these metrics. In implementing this strategy, they have identified key timing degradations that occur when new design parameters are introduced during physical synthesis.
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