Pipeline Processing in Low-Density Parity-Check Codes Hardware Decoder
Low-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This paper concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased.