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Pipelined CPU Design With FPGA in Teaching Computer Architecture

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Executive Summary

This paper presents a pipelined CPU design project with a Field Programmable Gate Array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bitMIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. This paper is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This paper reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009.

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