Power-And Area-Efficient Single SISO Architecture of Turbo Decoder

Date Added: Jul 2009
Format: PDF

In this paper, the authors propose a power- and area-efficient architecture of Turbo decoder. In order to improve the nonfunctional performance metrics such as power consumption and area, they use the trade-off method between Bit Error Rate (BER) performance and the two non-functional performance metrics. The proposed architecture shows about 16.7% reduction in power consumption and about 22.5% reduction in area compared to the general architecture. In digital wireless communication systems, channel coding is used to restore the damaged bits to the original bits. Turbo coding is one of the best channel coding schemes in terms of Bit Error Rate (BER) performance. When it was invented, turbo coding was not practically used because of its computational complexity and large decoding latency.