Power-Aware FPGA Design

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Executive Summary

Power consumption requirements in new, autonomous, multimedia-savvy consumer products that can store, transmit, and receive information have catapulted system architects and board and chip designers into a new realm. Even when designers attempted to reduce system power consumption, their approaches were not comprehensive and focused enough to achieve optimal results. The goal of this paper is to examine each design step and component of system power with the purpose of providing techniques to reduce wasteful power consumption. These techniques cover system partitioning, chip design, and board layout. The proposed design techniques cover RTL coding, arithmetic architecture power-profiling, and place-and-route hints. Some of these techniques may seem antiquated, but they have been revisited to fit the profile of applications required by most of the new consumer products targeting low-power FPGAs.

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