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As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-chip communication. The tight delay requirements faced by on-chip networks have resulted in prior microarchitectures being largely performance-driven. While performance is a critical metric, on-chip networks are also extremely power-constrained. In this paper, the authors investigate on-chip network microarchitectures from a power-driven perspective. They first analyze the power dissipation of existing network microarchitectures, highlighting insights that prompt people to devise several power-efficient network microarchitectures: Segmented crossbar, cut-through crossbar and write-through buffer.
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