Power Optimized Differential Conditional Capturing Flip-Flop for Clock Distribution Network
The operation of low/full swing LC resonant clocking scheme helps in reducing the overall power of the system by introducing a modern new flip-flop. The proposed dual mode Low/Full-swing differential Conditional Capturing Flip-Flop (LF-CCFF) operates with a low/full-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The functionality of the proposed (LF-CC) flip-flop was verified at extreme corners through simulation with parasitic extracted from layout. The LF-CCFF enables 5.5% reduction in power compared to the single mode full-swing flip-flop with 26% area overhead.