Date Added: Jul 2010
Now days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully Programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports smart instruction set, I/O port, UART, on-chip clocking to provide a range of frequencies, RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx.