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The authors propose a novel wear-leveling algorithm for the hybrid main memory architecture which exploits both fast read and write speed of DRAM and low power consumption and high density of PRAM. The wear-leveling algorithm consists of three techniques: DRAM buffering for reducing the write count, multiple data swapping for evening out the write count among all pages, and data shifting evening out the write count among all pages and lines. In order to evaluate performance, they implement a PIN-based wear-leveling simulator. In SPEC CPU2006, their proposed schemes can reduce the write count and maintain the write count equally among all pages and lines with little additional overhead.
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