Hardware

Process Induced Random Variation Models of Nanoscale MOS Performance: Efficient Tool for the Nanoscale Regime Analog/mixed Signal CMOS Statistical/variability Aware Design

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Executive Summary

In this paper, the novel models of random variation in Ids which is a key parameter of any MOS transistor, have been proposed in this paper as the probability density functions. Both triode and saturation regions have been explored. Unlike the previous researches, this paper has been performed based upon the up to dated nanoscale regime MOS equations. The proposed models for both regions have been verified at 65 nm technology by using the Monte Carlo simulation and the Kolmogorov-Smirnof goodness of fit test (KS-test).

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