Date Added: Jan 2011
Banking a processor cache enables non-conflicting reads to occur simultaneously, similar to having multiple read ports. However, bank conflicts expose this faux read port when two accesses must be serialized. The authors propose BARS, Banked Array of Redundant SRAMs, to emulate a multi-ported cache without paying the high price for true multiple ports. BARS is influenced directly by RAID techniques for high performance reliable disk storage. While the driving motivation for BARS is to reduce bank conflicts, it can also be used to increase reliability against errors while still maintaining excellent performance.