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The performance of future many-core processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM architectures appears unlikely to suffice, being constrained by processor and DRAM pin-bandwidth density and by total DRAM chip power, including off-chip signaling, cross-chip interconnect, and bank access energy. In this paper, the authors redesign the DRAM main-memory system using a proposed monolithically integrated siliconphotonic technology and show that their Photonically Interconnected DRAM (PIDRAM) provides a promising solution to all of these issues.
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