Recent Trends in FPGA Architecture for Testing the Data Path Using BSCAN
Now-a-days most of the data-path appliances are designed and developed using the basic FPGA architectures. In this paper, a new architecture is proposed based on design of FPGA. This design issue is of vital so as to fix the FPGA architecture fit for a data-path circuit functioning. The proposed architecture has a hierarchical interconnection structural design through which a chip with an array of 1616 LC is considered so that the interconnection of the proposed design is tested, and certain circuit sample from the design of a practical digital system is thus implemented. A CMOS process layout with 0.6um is integrated with the proposed chip architecture.