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Trends in wireless communication systems are in the direction of multi-mode systems using different algorithms to implement the baseband processing and the channel decoding. Efficient implementation of such multi-mode support requires flexible hardware. The authors present design and implementation of a reconfigurable processing element for a multi-processor architecture catering to both turbo and LDPC decoding needs in the context of the WiMaX (IEEE 802.16e) standard for high-throughput applications. As a case study, they evaluate the performance of their Multi Processor System on Chip (MPSoC) architecture for a 2-D Torus/Mesh interconnect topology.
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