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In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based decimators. A multiplier less CIC decimator has been used to reduce the cost by reducing the multiplier requirement. Two computationally efficient equiripple polyphone decomposition structure based decimators have been to reduce the filter order and hardware complexity. The embedded multipliers, LUTs and BRAMs have been efficiently utilized to enhance the system performance and resource utilization.
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