Reconfigurable High Performance Fault Detectable AES by Using Composite Fields
With rapid increases in communication and network applications, cryptography has become a crucial issue to ensure the security of transmitted data. This paper provides an efficient VLSI architecture to increase the throughput and security of the Advanced Encryption Standard (AES) Algorithm. The existing architecture provide the Look up Table technique for the Subbytes and inverse Subbytes transformation used in AES algorithm, the authors' proposed technique uses combinational circuit and pipelining technique which increase the throughput and reduce the delay. This design proposes a new technique for implementing the S-box, which decides the speed and power of AES architecture and the basic components of this architecture is made completely fault detectable by using pseudo-nMOS technology and thereby increases the security of this system.