Reconfigurable Network on Chip Router for Image Processing Based Multiprocessor Applications
Real time Image Processing (I.P) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time standards call for high speeds, but for data intensive application such as IP algorithms require constant transfer of data between the logic cores. This would need either dedicated connections or additional bus controllers. Networks-on-Chip (NoC) provides a structured way of realizing interconnections on silicon, and obviate the limitations of a bus-based solution. This paper deals with the design and implementation of a NoC router targeted for an Image processing system consisting of different modules.