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Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology that is a potential universal memory that could replace SRAM in processor caches. This paper presents a novel approach for redesigning STT-RAM memory cells to reduce the high dynamic energy and slow write latencies. The authors lower the retention time by reducing the planar area of the cell, thereby reducing the write current, which they then use with CACTI to design caches and memories. They simulate quad-core processor designs using a combination of SRAM- and STT-RAM-based caches. Since ultra-low retention STT-RAM may lose data, the authors also provide a preliminary evaluation for a simple, DRAM- style refresh policy.
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