Storage

Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems

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Executive Summary

A Single Event Upset (SEU) on a memory module often causes a soft error of a computer system. Occurrence of SEUs in SRAM memories is becoming a critical issue as technology continues to shrink. In this paper, the authors propose a task scheduling approach for Reliable Cache Architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that their task scheduling approach achieved 47.7-99.9% less vulnerability than a conventional one.

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