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Technological evolution enables the integration of billions of transistors on a chip. As VLSI technology scales, and processing power continues to improve, inter-processor communication becomes a performance bottleneck. On-chip networks have been widely proposed as the interconnect fabric for high performance SoCs. Recently, NoC architectures are emerging as the candidate for highly scalable, reliable, and modular on-chip communication infrastructure platform. This paper proposes the Generalized Binary De Bruijn (GBDB) graph based on combinatorial application as a reliable and efficient network topology for a large NoC. The authors propose a deadlock free & reliable routing algorithm to detour a faulty channel between two adjacent switches.
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